1. Field of the Invention
This invention relates to an oscillator circuit, specifically to a ring oscillator circuit provided with a current mirror type current limit circuit.
2. Description of Related Art
A ring oscillator has been used as an oscillator circuit for the various kinds of semi-conductor integrated circuits. It is necessary to acquire a low frequency oscillator clock signal when the ring oscillator is used as the self-refreshing oscillator circuit in a memory circuit such as DRAM. The low frequency oscillation is acquired by suppressing the electric current of the ring oscillator using a current mirror type current limit circuit.
FIG. 3 shows a ring oscillator type oscillator circuit provided with a current mirror type current limit circuit. In this oscillator circuit, five CMOS inverters INV1, INV2, INV3, INV4 and INV5 are serially connected, and the output of the last inverter INV5 is fed back to the input of the first inverter INV1, configuring a ring oscillator.
A current mirror type current limit circuit 10 has a P-channel type MOS transistor PM1, a resistor circuit 20 including a plurality of N-channel type MOS transistors connected in series with a power supply voltage Vdd applied at the gate of each transistor, and an N-channel type MOS transistor NM1. The drain and the gate of the P-channel type MOS transistor PM1 are connected with each other and the source of the transistor is provided with the power supply voltage Vdd. Also, the drain of the P-channel type MOS transistor PM1 is connected to the resistor circuit 20. The drain and the gate of the N-channel type MOS transistor NM1 are connected with each other and the source of the transistor is provided with the ground voltage Vss. Also, the drain of the N-channel type MOS transistor NM1 is connected to the resistor circuit 20. The electric current going through the P-channel type MOS transistor PM1 and the N-channel type MOS transistor NM1 is adjusted by the resistance of the resistor circuit 20. The resistance of the resistor circuit 20 is adjustable according to the number of the N-channel type MOS transistors serially connected.
The gate of the P-channel type MOS transistor PM1 is connected to each gate of the P-channel type MOS transistors PM2, PM3, PM4, PM5, and PM6 that are formed at the side of the power supply voltage Vdd of each of the CMOS inverters. Therefore, each of the P-channel type MOS transistors PM2, PM3, PM4, PM5, and PM6 forms a current mirror with the P-channel type MOS transistor PM1 respectively, with each of the P-channel type MOS transistors PM2, PM3, PM4, PM5, and PM6 having the same electric current as that of the P-channel type MOS transistor PM1, which enables limiting the electric current.
The gate of the N-channel type MOS transistor NM1 is connected to each gate of the N-channel type MOS transistors NM2, NM3, NM4, NM5, and NM6 that are formed at the side of the ground voltage Vss of each of the CMOS inverters. Therefore, each of the N-channel type MOS transistors NM2, NM3, NM4, NM5, and NM6 forms a current mirror with the N-channel type MOS transistor NM1 respectively, with each of the N-channel type MOS transistors NM2, NM3, NM4, NM5, and NM6 having the same electric current as that of the N-channel type MOS transistor NM1, which enables limiting the electric current.
The output of the last CMOS inverter INV5 of the ring oscillator is applied to the gates of a P-channel type MOS transistor PM7 and an N-channel type MOS transistor NM7 of the outputting CMOS inverter INV6. The output of the CMOS inverter INV3, which is located two positions ahead of the last inverter INV5 of the ring oscillator, is applied to the gates of a P-channel type MOS transistor PM8 and an N-channel type MOS transistor NM8 of the same outputting CMOS inverter INV6.
The oscillation waveform is adjusted by eliminating the through current of the CMOS inverter INV6, which is achieved by switching the P-channel type, MOS transistor PM8 and the N-channel type MOS transistor NM8 earlier than the P-channel type MOS transistor PM7 and the N-channel type MOS transistor NM7 using the output of the CMOS inverter INV3. Furthermore, the output of the CMOS inverter INV6 is applied to the input terminal of the CMOS inverter INV7. An oscillation clock signal RCLK is acquired from the output of the CMOS inverter INV7.
A P-channel type MOS transistor PM9 formed at the output terminal of the first CMOS inverter INV1 and an N-channel type MOS transistor NM9 inserted to a current path of the CMOS inverter INV1 are both transistors for resetting controlled by a reset signal SRE.
FIGS. 4A–4C show the oscillation waveforms acquired from the circuit simulation of the oscillator circuit described above. FIG. 4A is a waveform of the output of the CMOS inverter INV3 at a node N5, FIG. 4B is a waveform of output of the last CMOS inverter INV5 at a node N7, and FIG. 4C is a waveform of the oscillation clock signal RCLK outputted from the CMOS inverter INV7 respectively. FIG. 4A also shows the voltage at a node N1, which is a connecting point of the gates of the P-channel type MOS transistors PM2, PM3, PM4, PM5, and PM6, as well as the voltage at a node N2, which is a connecting point of the gates the N-channel type MOS transistors NM2, NM3, NM4, NM5, and NM6.